1. Field of the Invention
The invention relates to flash memories, and more particularly to control integrated circuits of flash memories.
2. Description of the Related Art
A flash memory is a non-volatile memory that can be electrically erased and reprogrammed. Flash memories are primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. Flash memory costs far less than EEPROM and therefore has become a dominant memory device. Examples of applications include Personal Digital Assistants (PDA) and laptop computers, digital audio players, digital cameras and mobile phones.
A flash device comprises a control integrated circuit (hereinafter, control IC) and at least one flash integrated circuit (hereinafter, flash IC). The flash IC stores data, and the control IC sends access signals to the flash IC to direct the flash IC to access data. Referring to FIG. 1A, a block diagram of a NAND flash integrated circuit (hereinafter, NAND flash IC) 100 is shown. The NAND flash IC 100 comprises an input/output control circuit 102, an input/output circuit 104, a control core circuit 106, a page buffer 108, and a flash core circuit 110. The I/O control circuit 102 receives a plurality of access signals from a control IC (not shown). In one embodiment, the access signals comprise a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, and a read enable signal RE#. The I/O circuit 104 then latches commands CMD and addresses sent by the control IC according to instructions of the I/O control circuit 102, and directs the flash core circuit 110 to access data stored therein according to the latched addresses. Data output by the flash core circuit 110 is stored in the page buffer 108 and then delivered to the I/O circuit 104, and the I/O circuit 104 sends the data to the control IC via an I/O bus (such as the bus I/O[7:0]). FIGS. 1B and 1C respectively show timings of the access signals CE#, CLE, ALE, WE#, and an I/O bus for directing the NAND flash IC 100 to receive commands and addresses from a control IC. FIG. ID shows timings of the access signals CE#, CLE, ALE, WE#, and the I/O bus for directing the NAND flash IC 100 to receive data written thereto, and FIG. 1E shows timings of the access signals CE#, CLE, ALE, RE#, and the I/O bus for directing the flash IC 100 to read data written therefrom.
A control IC of a flash device may control data access of more than one NAND flash IC. The different NAND flash ICs may have different routing lengths and different routing loads, and therefore require different access timings. Thus, performance of the different NAND flash ICs is therefore degraded. A flash device mitigating the aforementioned disadvantages is therefore required.